This invention relates to a power-down circuit for dynamic MOS integrated circuits.
Dynamic or clocked circuits have been widely used in MOS integrated circuits. The chief advantages of dynamic logic are as follows: (1) The flip-flop can be formed with fewer MOS devices. (2) System timing problems are simplified. (3) Less chip area is required per logic function, resulting in a lower cost of per function. (4) Since power is dissipated only when the load device is on, the power consumption is lower.
In case a MOS integrated circuit is powered with a battery, the use of a power-down circuit is useful to prolong the life of the battery. In static MOS logic integrated circuits, power saving can be easily realized by ceasing clock signals during idling conditions without destroying data stored therein. However, in the dynamic MOS logic integrated circuits, if clock signals are stopped during idling conditions, all the functions will cease, resulting in a loss of stored information. For this reason, it has been difficult to operate dynamic MOS integrated circuit in a power-down mode without occurring a loss of stored data.